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ciii52001-3.5 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone iii device handbook volume 2 july 2012 subscribe iso 9001:2008 registered 1. cyclone iii device datasheet this chapter describes the electric characte ristics, switching characteristics, and i/o timing for cyclone ? iii devices. a glossary is also included for your reference. electrical characteristics the following sections provide information about the absolute maximum ratings, recommended operating conditions, dc charac teristics, and other specifications for cyclone iii devices. operating conditions when cyclone iii devices are implemented in a system, they are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of cyclone iii devices, system designers must consider the operating requirements in this document. cyclone iii devices are offered in commercial, industrial, and automotive grades. commercial devices are offered in ?6 (fastest), ?7, and ?8 speed grades. industrial and automotive devices are offered only in ?7 speed grade. 1 in this chapter, a prefix associated with th e operating temperature range is attached to the speed grades; commercial with ?c? pr efix, industrial with ?i? prefix, and automotive with ?a? prefix. commercial de vices are therefore indicated as c6, c7, and c8 per respective speed grades. indust rial and automotive devices are indicated as i7 and a7, respectively. absolute maximum ratings absolute maximum ratings de fine the maximum operating conditions for cyclone iii devices. the values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied at these conditions. table 1?1 lists the absolute maximum ratings for cyclone iii devices. july 2012 ciii52001-3.5
1?2 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 1 conditions beyond those listed in table 1?1 cause permanent damage to the device. additionally, device operation at the abso lute maximum ratings for extended periods of time has adverse effects on the device. maximum allowed overshoot or undershoot voltage during transitions, input signals may overshoot to the voltage listed in table 1?2 and undershoot to ?2.0 v for a magnitude of currents less than 100 ma and for periods shorter than 20 ns. table 1?2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. the maximum allowed overshoot duration is specified as percentage of high-time over the lifetime of the device. table 1?1. cyclone iii devices absolute maximum ratings (1) symbol parameter min max unit v ccint supply voltage for internal logic ?0.5 1.8 v v ccio supply voltage for output buffers ?0.5 3.9 v v cca supply voltage (analog) for phase-locked loop (pll) regulator ?0.5 3.75 v v ccd_pll supply voltage (digital) for pll ?0.5 1.8 v v i dc input voltage ?0.5 3.95 v i out dc output current, per pin ?25 40 ma v esdhbm electrostatic discharge voltage using the human body model ? 2000 v v esdcdm electrostatic discharge voltage using the charged device model ? 500 v t stg storage temperature ?65 150 c t j operating junction temperature ?40 125 c note to table 1?1 : (1) supply voltage specifications apply to voltage readin gs taken at the device pins with respect to ground, not at the power supply.
chapter 1: cyclone iii device datasheet 1?3 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 1 a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 4.2 v can only be at 4.2 v for 10.74% over th e lifetime of the device; for device lifetime of 10 years, this amounts to 10.74/10ths of a year. figure 1?1 shows the methodology to determine the overshoot duration. table 1?2. cyclone iii devices maximum allowed overshoot during transitions over a 10-year time frame (1) symbol parameter condition overshoot duration as % of high time unit v i ac input voltage v i = 3.95 v 100 % v i = 4.0 v 95.67 % v i = 4.05 v 55.24 % v i = 4.10 v 31.97 % v i = 4.15 v 18.52 % v i = 4.20 v 10.74 % v i = 4.25 v 6.23 % v i = 4.30 v 3.62 % v i = 4.35 v 2.1 % v i = 4.40 v 1.22 % v i = 4.45 v 0.71 % v i = 4.50 v 0.41 % v i = 4.60 v 0.14 % v i = 4.70 v 0.047 % note to table 1?2 : (1) figure 1?1 shows the methodology to determine th e overshoot duration. in the example in figure 1?1 , overshoot voltage is shown in red and is present on the input pin of the cyclone iii device at over 4.1 v but below 4.2 v. from table 1?1 , for an overshoot of 4.1 v, the per centage of high time for the oversh oot can be as high as 31.97% over a 10-year period. percentage of high time is calculated as ([delta t]/t ) 100. this 10-year period assumes the device is always turned on with 100% i/o toggle rate and 50% duty cycle signal. for lower i/o toggle rates and situations in which the device is in an idle state, lifetimes are increased. figure 1?1. cyclone iii devices overshoot duration 3.3 v 4.1 v 4.2 v t t
1?4 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 recommended operating conditions this section lists the functional operation limits for ac and dc parameters for cyclone iii devices. the st eady-state voltage and current values expected from cyclone iii devices are provided in table 1?3 . all supplies must be strictly monotonic without plateaus. table 1?3. cyclone iii devices recommended operating conditions (1) , (2) symbol parameter conditions min typ max unit v ccint (3) supply voltage for internal logic ? 1.15 1.2 1.25 v v ccio (3) , (4) supply voltage for output buffers, 3.3-v operation ? 3.135 3.3 3.465 v supply voltage for output buffers, 3.0-v operation ? 2.85 3 3.15 v supply voltage for output buffers, 2.5-v operation ? 2.375 2.5 2.625 v supply voltage for output buffers, 1.8-v operation ? 1.71 1.8 1.89 v supply voltage for output buffers, 1.5-v operation ? 1.425 1.5 1.575 v supply voltage for output buffers, 1.2-v operation ? 1.14 1.2 1.26 v v cca (3) supply (analog) voltage for pll regulator ? 2.375 2.5 2.625 v v ccd_pll (3) supply (digital) voltage for pll ? 1.15 1.2 1.25 v v i input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature for commercial use 0 ? 85 c for industrial use ?40 ? 100 c for extended temperature ?40 ? 125 c for automotive use ?40 ? 125 c t ramp power supply ramp time standard power-on reset (por) (5) 50 s ? 50 ms ? fast por (6) 50 s ? 3 ms ? i diode magnitude of dc current across pci-clamp diode when enabled ???10ma notes to table 1?3 : (1) v ccio for all i/o banks must be powered up during device operation. all v cca pins must be powered to 2.5 v ( even when plls are not used), and must be powered up and powered down at the same time. (2) v ccd_pll must always be connected to v ccint through a decoupling cap acitor and ferrite bead. (3) the v cc must rise monotonically. (4) all input buffers are powered by the v ccio supply. (5) por time for standard por ranges between 50?200 ms. each in dividual power supply should reach the recommended operating rang e within 50 ms. (6) por time for fast por ranges between 3?9 ms. each individual power su pply should reach the recomme nded operating range withi n 3 ms.
chapter 1: cyclone iii device datasheet 1?5 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 dc characteristics this section lists the i/o leakage current, pin capacitance, on-chip termination (oct) tolerance, and bus hold specifications for cyclone iii devices. supply current standby current is the current the device draw s after the device is configured with no inputs or outputs toggling and no activity in the device. use the excel-based early power estimator (epe) to get the supply cu rrent estimates for your design because these currents vary largely with the resources used. table 1?4 lists i/o pin leakage current for cyclone iii devices. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . bus hold bus hold retains the last valid logic state af ter the source driving it either enters the high impedance state or is removed. each i/o pin has an option to enable bus hold in user mode. bus hold is always disabled in configuration mode. table 1?5 lists bus hold specifications for cyclone iii devices. table 1?4. cyclone iii devices i/o pin leakage current (1) , (2) symbol parameter conditions min typ max unit i i input pin leakage current v i = 0 v to v cciomax ?10 ? 10 ? a i oz tristated i/o pin leakage current v o = 0 v to v cciomax ?10 ? 10 ? a notes to table 1?4 : (1) this value is specified fo r normal device operation. the value varies during device pow er-up. this applies for all v ccio settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 v). (2) 10 ? a i/o leakage current limit is applicable when the internal clamping diode is off. a higher current can be the observed when the diode is on. table 1?5. cyclone iii devices bus hold parameter (part 1 of 2) (1) parameter condition v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus-hold low, sustaining current v in > v il (maximum) 8 ? 12 ? 30?50?70?70? ? a bus-hold high, sustaining current v in < v il (minimum) ?8 ? ?12 ? ?30 ? ?50 ? ?70 ? ?70 ? ? a
1?6 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 oct specifications table 1?6 lists the variation of oct without calibration across process, temperature, and voltage. oct calibration is automatically performe d at device power-up for oct enabled i/os. table 1?7 lists the oct calibration a ccuracy at device power-up. bus-hold low, overdrive current 0 v < v in < v ccio ? 125 ? 175 ? 200 ? 300 ? 500 ? 500 ? a bus-hold high, overdrive current 0 v < v in < v ccio ? ?125 ? ?175 ? ?200 ? ?300 ? ?500 ? ?500 ? a bus-hold trip point ? 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 v note to table 1?5 : (1) the bus-hold trip points are based on calc ulated input voltages fr om the jedec standard. table 1?5. cyclone iii devices bus hold parameter (part 2 of 2) (1) parameter condition v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max table 1?6. cyclone iii devices series oct without calibration specifications description v ccio (v) resistance tolerance unit commercial max industrial and automotive max series oct without calibration 3.0 30 40 % 2.5 30 40 % 1.8 +40 50 % 1.5 +50 50 % 1.2 +50 50 % table 1?7. cyclone iii devices series oct with calibration at device power-up specifications description v ccio (v) calibration accuracy unit commercial max industrial and automotive max series oct with calibration at device power-up 3.0 10 10 % 2.5 10 10 % 1.8 10 10 % 1.5 10 10 % 1.2 10 10 %
chapter 1: cyclone iii device datasheet 1?7 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 the oct resistance may vary with the va riation of temperature and voltage after calibration at device power-up. use table 1?8 and equation 1?1 to determine the final oct resistance considering the variations after calibration at device power-up. table 1?8 lists the change percentage of th e oct resistance with voltage and temperature. table 1?8. cyclone iii devices oct variation after calibration at device power-up nominal voltage dr/dt (%/c) dr/dv (%/mv) 3.0 0.262 ?0.026 2.5 0.234 ?0.039 1.8 0.219 ?0.086 1.5 0.199 ?0.136 1.2 0.161 ?0.288 equation 1?1. (1) , (2) , (3) , (4) , (5) , (6) ? r v = (v 2 ? v 1 ) 1000 dr/dv (7) ? r t = (t 2 ? t 1 ) dr/dt (8) for ? r x < 0; mf x = 1/ (| ? r x |/100 + 1) (9) for ? r x > 0; mf x = ? r x /100 + 1 (10) mf = mf v mf t (11) r final = r initial mf (12) notes to equation 1?1 : (1) t 2 is the final temperature. (2) t 1 is the initial temperature. (3) mf is multiplication factor. (4) r final is final resistance. (5) r initial is initial resistance. (6) subscript refers to both v and t . (7) ? r v is variation of resi stance with voltage. (8) ? r t is variation of resist ance with temperature. (9) dr/dt is the change percentage of resistance wi th temperature after calibration at device power-up. (10) dr/dv is the change percentage of resistance with voltage after calibra tion at device power-up. (11) v 2 is final voltage. (12) v 1 is the initial voltage.
1?8 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 example 1?1 shows you the example to calculate the change of 50 ?? i/o impedance from 25c at 3.0 v to 85c at 3.15 v: pin capacitance table 1?9 lists the pin capacitance for cyclone iii devices. example 1?1. ? r v = (3.15 ? 3) 1000 ?0.026 = ?3.83 ? r t = (85 ? 25) 0.262 = 15.72 because ? r v is negative, mf v = 1 / (3.83/100 + 1) = 0.963 because ? r t is positive, mf t = 15.72/100 + 1 = 1.157 mf = 0.963 1.157 = 1.114 r final = 50 1.114 = 55.71 ? table 1?9. cyclone iii devices pin capacitance symbol parameter typical ? qfp typical ? fbga unit c iotb input capacitance on top/bottom i/o pins 7 6 pf c iolr input capacitance on left/right i/o pins 7 5 pf c lvdslr input capacitance on left/right i/o pins with dedicated lvds output 87pf c vreflr (1) input capacitance on left/right dual-purpose vref pin when used as v ref or user i/o pin 21 21 pf c vreftb (1) input capacitance on top/bottom dual-purpose vref pin when used as v ref or user i/o pin 23 (2) 23 (2) pf c clktb input capacitance on top/bottom dedicated clock input pins 76pf c clklr input capacitance on left/right dedicated clock input pins 6 5 pf notes to table 1?9 : (1) when vref pin is used as regular input or output, a reduced performance of toggle rate and t co is expected due to higher pin capacitance. (2) c vreftb for ep3c25 is 30 pf.
chapter 1: cyclone iii device datasheet 1?9 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 internal weak pull-up and weak pull-down resistor table 1?10 lists the weak pull-up and pull-down resistor values for cyclone iii devices. hot socketing table 1?11 lists the hot-socketing specifications for cyclone iii devices. table 1?10. cyclone iii devices internal weak pull-up and weak pull-down resistor (1) symbol parameter conditions min typ max unit r _pu value of i/o pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled v ccio = 3.3 v 5% (2) , (3) 72541k ? v ccio = 3.0 v 5% (2) , (3) 72847k ? v ccio = 2.5 v 5% (2) , (3) 83561k ? v ccio = 1.8 v 5% (2) , (3) 10 57 108 k ? v ccio = 1.5 v 5% (2) , (3) 13 82 163 k ? v ccio = 1.2 v 5% (2) , (3) 19 143 351 k ? r _pd value of i/o pin pull-down resistor before and during configuration v ccio = 3.3 v 5% (4) 61930k ? v ccio = 3.0 v 5% (4) 62236k ? v ccio = 2.5 v 5% (4) 62543k ? v ccio = 1.8 v 5% (4) 73571k ? v ccio = 1.5 v 5% (4) 850112k ? notes to table 1?10 : (1) all i/o pins have an option to enable weak pull-up except configurat ion, test, and jtag pin. weak pull-down feature is only available for jtag tck. (2) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . (3) r _pu = (v ccio ?v i )/i r_pu minimum condition: ?40c; v ccio = v cc + 5%, v i = v cc + 5% ? 50 mv; typical condition: 25c; v ccio = v cc , v i = 0 v; maximum condition: 125c; v ccio = v cc ? 5%, v i = 0 v; in which v i refers to the input voltage at the i/o pin. (4) r _pd = v i /i r_pd minimum condition: ?40c; v ccio = v cc + 5%, v i = 50 mv; typical condition: 25c; v ccio = v cc , v i = v cc ?5%; maximum condition: 125c; v ccio = v cc ? 5%, v i = v cc ? 5%; in which v i refers to the input voltage at the i/o pin. table 1?11. cyclone iii devices hot-socketing specifications symbol parameter maximum i iopin(dc) dc current per i/o pin 300 ? a i iopin(ac) ac current per i/o pin 8 ma (1) note to table 1?11 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |iiopin| = c dv/dt, in which c is i/o pin capaci tance and dv/dt is the slew rate.
1?10 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 schmitt trigger input cyclone iii devices support schmitt trigger input on tdi , tms , tck , nstatus , nconfig , nce , conf_done , and dclk pins. a schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate. table 1?12 lists the hysteresis specifications across supported v ccio range for schmitt trigger inputs in cyclone iii devices. i/o standard specifications the following tables list input voltage sensitivities (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by cyclone iii devices. table 1?13 through table 1?18 provide the i/o standard specifications for cyclone iii devices. table 1?12. hysteresis specifications for schmitt trigger input in cyclone iii devices symbol parameter conditions minimum typical maximum unit v schmitt hysteresis for schmitt trigger input v ccio = 3.3 v 200 ? ? mv v ccio = 2.5 v 200 ? ? mv v ccio = 1.8 v 140 ? ? mv v ccio = 1.5 v 110 ? ? mv table 1?13. cyclone iii devices single-ended i/o standard specifications (1) , (2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min 3.3-v lvttl (3) 3.135 3.3 3.465 ? 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3-v lvcmos (3) 3.135 3.3 3.465 ? 0.8 1.7 3.6 0.2 v ccio ? 0.2 2 ?2 3.0-v lvttl (3) 2.85 3.0 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.45 2.4 4 ?4 3.0-v lvcmos (3) 2.85 3.0 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.2 v ccio ? 0.2 0.1 ?0.1 2.5-v lvttl and lvcmos (3) 2.375 2.5 2.625 ?0.3 0.7 1.7 3.6 0.4 2.0 1 ?1 1.8-v lvttl and lvcmos 1.71 1.8 1.89 ?0.3 0.35 * v ccio 0.65 * v ccio 2.25 0.45 v ccio ? 0.45 2?2 1.5-v lvcmos 1.425 1.5 1.575 ?0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2?2 1.2-v lvcmos 1.14 1.2 1.26 ?0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2?2 3.0-v pci 2.85 3.0 3.15 ? 0.3 * v ccio 0.5 * v ccio v ccio + 0.3 0.1 * v ccio 0.9 * v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3.0 3.15 ? 0.35* v ccio 0.5 * v ccio v ccio + 0.3 0.1 * v ccio 0.9 * v ccio 1.5 ?0.5 notes to table 1?13 : (1) for voltage referenced receiver input w aveform and explanation of terms used in table 1?13 , refer to ?single-ended voltage referenced i/o standard? in ?glossary? on page 1?27 . (2) ac load cl = 10 pf. (3) for more detail about interfacin g cyclone iii devices with 3. 3/3.0/2.5-v lvttl/lvcmos i/o standards, refer to an 447: interfacing cyclone iii devices with 3.3/3.0/2.5-v lvttl and lvcmos i/o systems .
chapter 1: cyclone iii device datasheet 1?11 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 table 1?14. cyclone iii devices single-ended sstl and hstl i/o reference voltage specifications (1) i/o standard v ccio (v) v ref (v) v tt (v) (2) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95 hstl-15 class i, ii 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79 hstl-12 class i, ii 1.14 1.2 1.26 0.48 * v ccio (3) 0.5 * v ccio (3) 0.52 * v ccio (3) ? 0.5 * v ccio ? 0.47 * v ccio (4) 0.5 * v ccio (4) 0.53 * v ccio (4) notes to table 1?14 : (1) for an explanation of terms used in table 1?14 , refer to ?glossary? on page 1?27 . (2) v tt of transmitting device must track v ref of the receiving device. (3) value shown refers to dc input reference voltage, v ref(dc) . (4) value shown refers to ac input reference voltage, v ref(ac) . table 1?15. cyclone iii devices single-ended sstl and hstl i/o standards signal specifications i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max min max min max max min sstl-2 class i ? v ref ? 0.18 v ref + 0.18 ?? v ref ? 0.35 v ref + 0.35 ? v tt ? 0.57 v tt + 0.57 8.1 ?8.1 sstl-2 class ii ? v ref ? 0.18 v ref + 0.18 ?? v ref ? 0.35 v ref + 0.35 ? v tt ? 0.76 v tt + 0.76 16.4 ?16.4 sstl-18 class i ? v ref ? 0.125 v ref + 0.125 ?? v ref ? 0.25 v ref + 0.25 ? v tt ? 0.475 v tt + 0.475 6.7 ?6.7 sstl-18 class ii ? v ref ? 0.125 v ref + 0.125 ?? v ref ? 0.25 v ref + 0.25 ?0.28 v ccio ? 0.28 13.4 ?13.4 hstl-18 class i ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 8?8 hstl-18 class ii ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 16 ?16 hstl-15 class i ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 8?8 hstl-15 class ii ? v ref ? 0.1 v ref + 0.1 ?? v ref ? 0.2 v ref + 0.2 ?0.4 v ccio ? 0.4 16 ?16 hstl-12 class i ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 ?0.24 v ref ? 0.15 v ref + 0.15 v ccio + 0.24 0.25 v ccio 0.75 v ccio 8?8 hstl-12 class ii ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 ?0.24 v ref ? 0.15 v ref + 0.15 v ccio + 0.24 0.25 v ccio 0.75 v ccio 14 ?14
1?12 chapter 1: cyclone iii device datasheet electrical characteristics cyclone iii device handbook july 2012 altera corporation volume 2 f for more illustrations of receiver input and transmitter output waveforms, and for other differential i/o standards, refer to the high-speed differential interfaces in cyclone iii devices chapter . table 1?16. cyclone iii devices differential sstl i/o standard specifications (1) i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.36 v ccio v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.7 v cci o v ccio /2 ? 0.125 ? v ccio /2 + 0.125 sstl-18 class i, ii 1.7 1.8 1.90 0.25 v ccio v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v cci o v ccio /2 ? 0.125 ? v ccio /2 + 0.125 note to table 1?16 : (1) differential sstl requires a v ref input. table 1?17. cyclone iii devices differential hstl i/o standard specifications (1) i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max mi n max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.85 ? 0.95 0.85 ? 0.95 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.71 ? 0.79 0.71 ? 0.79 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio 0.48 * v ccio ? 0.52 * v ccio 0.48 * v ccio ? 0.52 * v ccio 0.3 0.48 * v ccio note to table 1?17 : (1) differential hstl requires a v ref input. table 1?18. cyclone iii devices differential i/o standard specifications (1) (part 1 of 2) i/o standard v ccio (v) v id (mv) v icm (v) (2) v od (mv) (3) v os (v) (3) min typ max min max min condition max min typ max min typ max lvpecl (row i/os) (4) 2.375 2.5 2.625 100 ? 0.05 d max ??? 500 mbps 1.80 ?? ? ? ? ? 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 lvpecl (column i/os) (4) 2.375 2.5 2.625 100 ? 0.05 d max ?? 500 mbps 1.80 ?? ? ? ? ? 0.55 500 mbps ? d max ?? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 lvds (row i/os) 2.375 2.5 2.625 100 ? 0.05 d max ?? 500 mbps 1.80 247 ? 600 1.125 1.25 1.375 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55
chapter 1: cyclone iii device datasheet 1?13 electrical characteristics july 2012 altera corporation cyclone iii device handbook volume 2 lvds (column i/os) 2.375 2.5 2.625 100 ? 0.05 d max ? 500 mbps 1.80 247 ? 600 1.125 1.25 1.375 0.55 500 mbps ? d max ? 700 mbps 1.80 1.05 d max > 700 mbps 1.55 blvds (row i/os) (5) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? blvds (column i/os) (5) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? mini-lvds (row i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 300 ? 600 1.0 1.2 1.4 mini-lvds (column i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 300 ? 600 1.0 1.2 1.4 rsds ? (row i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.5 rsds (column i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.5 ppds ? (row i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.4 ppds (column i/os) (6) 2.375 2.5 2.625 ? ? ? ? ? 100 200 600 0.5 1.2 1.4 notes to table 1?18 : (1) for an explanation of terms used in table 1?18 , refer to ?transmitter output waveform? in ?glossary? on page 1?27 . (2) v in range: 0 v ? v in ? 1.85 v. (3) r l range: 90 ? r l ? 110 ? . (4) lvpecl input standard is only supported at clock input. output standard is not supported. (5) no fixed v in , v od , and v os specifications for blvds. they ar e dependent on the system topology. (6) mini-lvds, rsds, and ppds stan dards are only supported at the output pins for cyclone iii devices. table 1?18. cyclone iii devices differential i/o standard specifications (1) (part 2 of 2) i/o standard v ccio (v) v id (mv) v icm (v) (2) v od (mv) (3) v os (v) (3) min typ max min max min condition max min typ max min typ max
1?14 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 power consumption you can use the following methods to estimate power for a design: the excel-based epe. the quartus ii powerplay power analyzer feature. the interactive excel-based epe is used prior to designing the device to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the de sign after place-and- route is complete. the powerplay power analyzer can apply a combination of user- entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. f for more information about power estimation tools, refer to the early power estimator user guide and the powerplay power analysis chapter in volume 3 of the quartus ii handboo k. switching characteristics this section provides the performance characteristics of the core and periphery blocks for cyclone iii devices. all data is final and is based on actual silicon characterization and testing. these numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. core performance specifications clock tree specifications table 1?19 lists the clock tree specifications for cyclone iii devices. table 1?19. cyclone iii devices clock tree performance device performance unit c6 c7 c8 ep3c5 500 437.5 402 mhz ep3c10 500 437.5 402 mhz ep3c16 500 437.5 402 mhz ep3c25 500 437.5 402 mhz ep3c40 500 437.5 402 mhz ep3c55 500 437.5 402 mhz ep3c80 500 437.5 402 mhz ep3c120 (1) 437.5 402 mhz note to table 1?19 : (1) ep3c120 offered in c7, c8, and i7 grades only.
chapter 1: cyclone iii device datasheet 1?15 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 pll specifications table 1?20 describes the pll specifications for cyclone iii devices when operating in the commercial junction temperature range (0c to 85c), the industrial junction temperature range (?40c to 100c), and th e automotive junction temperature range (?40cto 125c). for more information about pll block, refer to ?pll block? in ?glossary? on page 1?27 . table 1?20. cyclone iii devices pll specifications (1) (part 1 of 2) symbol parameter min typ max unit f in (2) input clock frequency 5 ? 472.5 mhz f inpfd pfd input frequency 5 ? 325 mhz f vco (3) pll internal vco operating range 600 ? 1300 mhz f induty input clock duty cycle 40 ? 60 % t injitter_ccj (4) input clock cycle-to-cycle jitter for f inpfd ? 100 mhz ? ? 0.15 ui input clock cycle-to-cycle jitter for f inpfd < 100 mhz ? ? 750 ps f out_ext (external clock output) (2) pll output frequency ? ? 472.5 mhz f out (to global clock) pll output frequency (?6 speed grade) ? ? 472.5 mhz pll output frequency (?7 speed grade) ? ? 450 mhz pll output frequency (?8 speed grade) ? ? 402.5 mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t lock time required to lock from end of device configuration ? ? 1 ms t dlock time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) ?? 1 ms t outjitter_period_dedclk (5) dedicated clock output period jitter f out ? 100 mhz ? ? 300 ps f out < 100 mhz ? ? 30 mui t outjitter_ccj_dedclk (5) dedicated clock output cycle-to-cycle jitter f out ? 100 mhz ? ? 300 ps f out < 100 mhz ? ? 30 mui t outjitter_period_io (5) regular i/o period jitter f out ? 100 mhz ? ? 650 ps f out < 100 mhz ? ? 75 mui t outjitter_ccj_io (5) regular i/o cycle-to-cycle jitter f out ? 100 mhz ? ? 650 ps f out < 100 mhz ? ? 75 mui t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on areset signal. 10 ? ? ns t configpll time required to reconfigure scan chains for plls ? 3.5 (6) ? scanclk cycles
1?16 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 embedded multiplier specifications table 1?21 describes the embedded multiplier specifications for cyclone iii devices. memory block specifications table 1?22 describes the m9k memory block specifications for cyclone iii devices. configuration and jtag specifications table 1?23 lists the configuration mode specifications for cyclone iii devices. f scanclk scanclk frequency ? ? 100 mhz notes to table 1?20 : (1) v ccd_pll should always be connected to v ccint through decoupling capacitor and ferrite bead. (2) this parameter is limited in the quartu s ii software by the i/o maximum frequency. the maximum i/o frequency is different fo r each i/o standard. (3) the v co frequency reported by the quartus ii softw are in the pll summary section of the co mpilation report takes in to consideration th e v co post-scale counter k value. therefore, if the co unter k has a value of 2, the freque ncy reported can be lower than the f vco specification. (4) a high input jitter directly affects the pll output jitter. to have low pll output clock jitte r, you must provide a clean cl ock source, which is less than 200 ps. (5) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the ou tput jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. (6) with 100 mhz scanclk frequency. table 1?20. cyclone iii devices pll specifications (1) (part 2 of 2) symbol parameter min typ max unit table 1?21. cyclone iii devices embedded multiplier specifications mode resources used performance unit number of multipliers c6 c7, i7, a7 c8 9 9-bit multiplier 1 340 300 260 mhz 18 18-bit multiplier 1 287 250 200 mhz table 1?22. cyclone iii devices memory block performance specifications memory mode resources used performance les m9k memory c6 c7, i7, a7 c8 unit m9k block fifo 256 36 47 1 315 274 238 mhz single-port 256 36 0 1 315 274 238 mhz simple dual-port 256 36 clk 0 1 315 274 238 mhz true dual port 512 18 single clk 0 1 315 274 238 mhz table 1?23. cyclone iii devices configuration mode specifications programming mode dclk f max unit passive serial (ps) 133 mhz fast passive parallel (fpp) (1) 100 mhz note to table 1?23 : (1) ep3c40 and smaller density members support 133 mhz.
chapter 1: cyclone iii device datasheet 1?17 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 table 1?24 lists the active configuration mode specifications for cyclone iii devices. table 1?25 lists the jtag timing parameters and values for cyclone iii devices. periphery performance this section describes periphery performanc e, including high-speed i/o, external memory interface, and ioe programmable delay. i/o performance supports several system interfacing, for example, the high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. i/o using the sstl-18 class i termination standard ca n achieve up to the stated ddr2 sdram interfacing speeds with typical ddr sdram memory interface setup. i/o using general-purpose i/o standards such as 3. 0-, 2.5-, 1.8-, or 1.5-lvttl/lvcmos are capable of a typical 200 mhz interfacing frequency with a 10 pf load. 1 actual achievable frequency depends on de sign- and system-specific factors. perform hspice/ibis simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. table 1?24. cyclone iii devices active configuration mode specifications programming mode dclk range unit active parallel (ap) 20 ? 40 mhz active serial (as) 20 ? 40 mhz table 1?25. cyclone iii devices jtag timing parameters (1) symbol parameter min max unit t jcp tck clock period 40 ? ns t jch tck clock high time 20 ? ns t jcl tck clock low time 20 ? ns t jpsu_tdi jtag port setup time for tdi 1 ? ns t jpsu_tms jtag port setup time for tms 3 ? ns t jph jtag port hold time 10 ? ns t jpco jtag port clock to output (2) ?15ns t jpzx jtag port high impedance to valid output (2) ?15ns t jpxz jtag port valid output to high impedance (2) ?15ns t jssu capture register setup time 5 ? ns t jsh capture register hold time 10 ? ns t jsco update register clock to output ? 25 ns t jszx update register high impedance to valid output ? 25 ns t jsxz update register valid output to high impedance ? 25 ns notes to table 1?25 : (1) for more information abou t jtag waveforms, refer to ?jtag waveform? in ?glossary? on page 1?27 . (2) the specification is shown for 3.3-, 3.0-, and 2.5-v lv ttl/lvcmos operation of jtag pins. for 1.8-v lvttl/lvcmos and 1.5-v lvcmos, the jtag port clock to output time is 16 ns.
1?18 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 high-speed i/o specifications table 1?26 through table 1?31 list the high-speed i/o timi ng for cyclone iii devices. for definitions of high-speed timing specifications, refer to ?glossary? on page 1?27 . table 1?26. cyclone iii devices rsds transmitter timing specifications (1) , (2) symbol modes c6 c7, i7 c8, a7 unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 180 5 ? 155.5 5 ? 155.5 mhz 8 5 ? 180 5 ? 155.5 5 ? 155.5 mhz 7 5 ? 180 5 ? 155.5 5 ? 155.5 mhz 4 5 ? 180 5 ? 155.5 5 ? 155.5 mhz 2 5 ? 180 5 ? 155.5 5 ? 155.5 mhz 1 5 ? 360 5 ? 311 5 ? 311 mhz device operation in mbps 10 100 ? 360 100 ? 311 100 ? 311 mbps 8 80 ? 360 80 ? 311 80 ? 311 mbps 7 70 ? 360 70 ? 311 70 ? 311 mbps 4 40 ? 360 40 ? 311 40 ? 311 mbps 2 20 ? 360 20 ? 311 20 ? 311 mbps 1 10 ? 360 10 ? 311 10 ? 311 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 % tccs ? ? ? 200 ? ? 200 ? ? 200 ps output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ps t rise 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5pf ? 500 ? ? 500 ? ? 500 ? ps t lock (3) ???1??1??1ms notes to table 1?26 : (1) applicable for true rsds and emulated rsds_e_3r transmitter. (2) true rsds transmitter is only supported at output pin of row i/o (banks 1, 2, 5, and 6). emul ated rsds transmitter is suppor ted at the output pin of all i/o banks. (3) t lock is the time required for the pll to lock from the end of device configuration. table 1?27. cyclone iii devices emulated rsds_e_1r transmitter timing specifications (1) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 85 5 ? 85 5 ? 85 mhz 8 5 ? 85 5 ? 85 5 ? 85 mhz 7 5 ? 85 5 ? 85 5 ? 85 mhz 4 5 ? 85 5 ? 85 5 ? 85 mhz 2 5 ? 85 5 ? 85 5 ? 85 mhz 1 5 ? 170 5 ? 170 5 ? 170 mhz
chapter 1: cyclone iii device datasheet 1?19 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 device operation in mbps 10 100 ? 170 100 ? 170 100 ? 170 mbps 8 80 ? 170 80 ? 170 80 ? 170 mbps 7 70 ? 170 70 ? 170 70 ? 170 mbps 4 40 ? 170 40 ? 170 40 ? 170 mbps 2 20 ? 170 20 ? 170 20 ? 170 mbps 1 10 ? 170 10 ? 170 10 ? 170 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 % tccs ? ? ? 200 ? ? 200 ? ? 200 ps output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ps t rise 20 ? 80%, c load = 5 pf ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5 pf ? 500 ? ? 500 ? ? 500 ? ps t lock (2) ???1??1??1ms notes to table 1?27 : (1) emulated rsds_e_1r transmitter is suppor ted at the output pin of all i/o banks. (2) t lock is the time required for the pll to lock from the end of device configuration. table 1?27. cyclone iii devices emulated rsds_e_1r transmitter timing specifications (1) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 unit min typ max min typ max min typ max table 1?28. cyclone iii devices mini-lvds transmitter timing specifications (1) , (2) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 5 ? 200 5 ? 155.5 5 ? 155.5 mhz 8 5 ? 200 5 ? 155.5 5 ? 155.5 mhz 7 5 ? 200 5 ? 155.5 5 ? 155.5 mhz 4 5 ? 200 5 ? 155.5 5 ? 155.5 mhz 2 5 ? 200 5 ? 155.5 5 ? 155.5 mhz 1 5 ? 400 5 ? 311 5 ? 311 mhz device operation in mbps 10 100 ? 400 100 ? 311 100 ? 311 mbps 8 80 ? 400 80 ? 311 80 ? 311 mbps 7 70 ? 400 70 ? 311 70 ? 311 mbps 4 40 ? 400 40 ? 311 40 ? 311 mbps 2 20 ? 400 20 ? 311 20 ? 311 mbps 1 10 ? 400 10 ? 311 10 ? 311 mbps t duty ? 45 ? 55 45 ? 55 45 ? 55 % tccs ? ? ? 200 ? ? 200 ? ? 200 ps
1?20 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 output jitter (peak to peak) ? ? ? 500 ? ? 500 ? ? 550 ps t rise 20 ? 80%, c load = 5 pf ? 500 ? ? 500 ? ? 500 ? ps t fall 20 ? 80%, c load = 5 pf ? 500 ? ? 500 ? ? 500 ? ps t lock (3) ???1??1??1ms notes to table 1?28 : (1) applicable for true and em ulated mini-lvds transmitter. (2) true mini-lvds transmitter is only support ed at the output pin of row i/o (banks 1, 2, 5, and 6). emulated mini-lvds transmi tter is supported at the output pin of all i/o banks. (3) t lock is the time required for the pll to lock from the end of device configuration. table 1?28. cyclone iii devices mini-lvds transmitter timing specifications (1) , (2) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 unit min typ max min typ max min typ max
chapter 1: cyclone iii device datasheet 1?21 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 table 1?29. cyclone iii devices true lvds transmitter timing specifications (1) symbol modes c6 c7, i7 c8, a7 unit min max min max min max f hsclk (input clock frequency) 10 5 420 5 370 5 320 mhz 8 5 420 5 370 5 320 mhz 7 5 420 5 370 5 320 mhz 4 5 420 5 370 5 320 mhz 2 5 420 5 370 5 320 mhz 1 5 420 5 402.5 5 402.5 mhz hsiodr 10 100 840 100 740 100 640 mbps 8 80 840 80 740 80 640 mbps 7 70 840 70 740 70 640 mbps 4 40 840 40 740 40 640 mbps 2 20 840 20 740 20 640 mbps 1 10 420 10 402.5 10 402.5 mbps t duty ? 455545554555% tccs ? ? 200 ? 200 ? 200 ps output jitter (peak to peak) ? ? 500 ? 500 ? 550 ps t lock (2) ? ?1?1?1ms notes to table 1?29 : (1) true lvds transmitter is only supported at th e output pin of row i/o (banks 1, 2, 5, and 6). (2) t lock is the time required for the pll to lock from the end of device configuration. table 1?30. cyclone iii devices emulated lvds transmitter timing specifications (1) (part 1 of 2) symbol modes c6 c7, i7 c8, a7 unit min max min max min max f hsclk (input clock frequency) 10 5 320 5 320 5 275 mhz 8 5 320 5 320 5 275 mhz 7 5 320 5 320 5 275 mhz 4 5 320 5 320 5 275 mhz 2 5 320 5 320 5 275 mhz 1 5 402.5 5 402.5 5 402.5 mhz hsiodr 10 100 640 100 640 100 550 mbps 8 80 640 80 640 80 550 mbps 7 70 640 70 640 70 550 mbps 4 40 640 40 640 40 550 mbps 2 20 640 20 640 20 550 mbps 1 10 402.5 10 402.5 10 402.5 mbps t duty ? 455545554555% tccs ? ? 200 ? 200 ? 200 ps
1?22 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 external memory interface specifications cyclone iii devices support ex ternal memory interfaces up to 200 mhz. the external memory interfaces for cyclone iii devices ar e auto-calibrating and easy to implement. f for more information about external memo ry system performance specifications, board design guidelines, timing analysis, simulation, and debugging information, refer to literature: external memory interfaces . output jitter (peak to peak) ? ? 500 ? 500 ? 550 ps t lock (2) ? ?1?1?1ms notes to table 1?30 : (1) emulated lvds transmitter is support ed at the output pin of all i/o banks. (2) t lock is the time required for the pll to lock from the end of device configuration. table 1?31. cyclone iii devices lvds receiver timing specifications (1) symbol modes c6 c7, i7 c8, a7 unit min max min max min max f hsclk (input clock frequency) 10 5 437.5 5 370 5 320 mhz 8 5 437.5 5 370 5 320 mhz 7 5 437.5 5 370 5 320 mhz 4 5 437.5 5 370 5 320 mhz 2 5 437.5 5 370 5 320 mhz 1 5 437.5 5 402.5 5 402.5 mhz hsiodr 10 100 875 100 740 100 640 mbps 8 80 875 80 740 80 640 mbps 7 70 875 70 740 70 640 mbps 4 40 875 40 740 40 640 mbps 2 20 875 20 740 20 640 mbps 1 10 437.5 10 402.5 10 402.5 mbps sw ? ? 400 ? 400 ? 400 ps input jitter tolerance ? ? 500 ? 500 ? 550 ps t lock (2) ? ?1?1?1ms notes to table 1?31 : (1) lvds receiver is supported at all banks. (2) t lock is the time required for the pll to lock from the end of device configuration. table 1?30. cyclone iii devices emulated lvds transmitter timing specifications (1) (part 2 of 2) symbol modes c6 c7, i7 c8, a7 unit min max min max min max
chapter 1: cyclone iii device datasheet 1?23 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 table 1?32 lists the fpga sampling window specifications for cyclone iii devices. table 1?33 lists the transmitter channel-to-channe l skew specificatio ns for cyclone iii devices. table 1?32. cyclone iii devices fpga sampling window (sw) requirement ? read side (1) memory standard column i/os row i/os wraparound mode setup hold setup hold setup hold c6 ddr2 sdram 580 550 690 640 850 800 ddr sdram 585 535 700 650 870 820 qdrii sram 785 735 805 755 905 855 c7 ddr2 sdram 705 650 770 715 985 930 ddr sdram 675 620 795 740 970 915 qdrii sram 900 845 910 855 1085 1030 c8 ddr2 sdram 785 720 930 870 1115 1055 ddr sdram 800 740 915 855 1185 1125 qdrii sram 1050 990 1065 1005 1210 1150 i7 ddr2 sdram 765 710 855 800 1040 985 ddr sdram 745 690 880 825 1000 945 qdrii sram 945 890 955 900 1130 1075 a7 ddr2 sdram 805 745 1020 960 1145 1085 ddr sdram 880 820 955 935 1220 1160 qdrii sram 1090 1030 1105 1045 1250 1190 note to table 1?32 : (1) column i/os refer to top and bottom i/os. row i/os refer to righ t and left i/os. wraparound mode refers to the combination o f column and row i/os. table 1?33. cyclone iii devices transmitter channel-to-channel skew (tccs) ? write side (1) (part 1 of 2) memory standard i/o standard column i/os (ps) row i/os (ps) wraparound mode (ps) lead lag lead lag lead lag c6 ddr2 sdram sstl-18 class i 790 380 790 380 890 480 sstl-18 class ii 870 490 870 490 970 590 ddr sdram sstl-2 class i 750 320 750 320 850 420 sstl-2 class ii 860 350 860 350 960 450 qdrii sram 1.8 v hstl class i 780 410 780 410 880 510 1.8 v hstl class ii 830 510 830 510 930 610 c7
1?24 chapter 1: cyclone iii device datasheet switching characteristics cyclone iii device handbook july 2012 altera corporation volume 2 table 1?34 lists the memory output clock jitter specifications for cyclone iii devices. ddr2 sdram sstl-18 class i 915 410 915 410 1015 510 sstl-18 class ii 1025 545 1025 545 1125 645 ddr sdram sstl-2 class i 880 340 880 340 980 440 sstl-2 class ii 1010 380 1010 380 1110 480 qdrii sram 1.8 v hstl class i 910 450 910 450 1010 550 1.8 v hstl class ii 1010 570 1010 570 1110 670 c8 ddr2 sdram sstl-18 class i 1040 440 1040 440 1140 540 sstl-18 class ii 1180 600 1180 600 1280 700 ddr sdram sstl-2 class i 1010 360 1010 360 1110 460 sstl-2 class ii 1160 410 1160 410 1260 510 qdrii sram 1.8 v hstl class i 1040 490 1040 490 1140 590 1.8 v hstl class ii 1190 630 1190 630 1290 730 i7 ddr2 sdram sstl-18 class i 961 431 961 431 1061 531 sstl-18 class ii 1076 572 1076 572 1176 672 ddr sdram sstl-2 class i 924 357 924 357 1024 457 sstl-2 class ii 1061 399 1061 399 1161 499 qdrii sram 1.8 v hstl class i 956 473 956 473 1056 573 1.8 v hstl class ii 1061 599 1061 599 1161 699 a7 ddr2 sdram (2) sstl-18 class i 1092 462 1092 462 1192 562 sstl-18 class ii 1239 630 1239 630 1339 730 ddr sdram sstl-2 class i 1061 378 1061 378 1161 478 sstl-2 class ii 1218 431 1218 431 1318 531 qdrii sram 1.8 v hstl class i 1092 515 1092 515 1192 615 1.8 v hstl class ii 1250 662 1250 662 1350 762 notes to table 1?33 : (1) column i/o banks refer to top and bottom i/os. row i/o banks refer to right and left i/os. wraparound mode refers to the com bination of column and row i/os. (2) for ddr2 sdram write timing performan ce on columns i/o for c8 an d a7 devices, 97.5 degree phase offset is required. table 1?33. cyclone iii devices transmitter channel-to-channel skew (tccs) ? write side (1) (part 2 of 2) memory standard i/o standard column i/os (ps) row i/os (ps) wraparound mode (ps) lead lag lead lag lead lag table 1?34. cyclone iii devices memory output clock jitter specifications (1) , (2) (part 1 of 2) parameter symbol min max unit clock period jitter t jit(per) -125 125 ps cycle-to-cycle period jitter t jit(cc) -200 200 ps
chapter 1: cyclone iii device datasheet 1?25 switching characteristics july 2012 altera corporation cyclone iii device handbook volume 2 duty cycle distortion specifications table 1?35 lists the worst case duty cycle di stortion for cyclone iii devices. oct calibration timing specification table 1?36 lists the duration of calibration for series oct with calibration at device power-up for cyclone iii devices. ioe programmable delay table 1?37 and table 1?38 list ioe programmable dela y for cyclone iii devices. duty cycle jitter t jit(duty) -150 150 ps notes to table 1?34 : (1) the memory output clock jitter measurem ents are for 200 consecutive clock cycles, as specified in the jedec ddr2 standard. (2) the clock jitter specification ap plies to memory output clock pins generated us ing ddio circuits clocked by a pll output rou ted on a global clock network. table 1?34. cyclone iii devices memory output clock jitter specifications (1) , (2) (part 2 of 2) parameter symbol min max unit table 1?35. duty cycle distortion on cyclone iii devices i/o pins (1) , (2) symbol c6 c7, i7 c8, a7 unit min max min max min max output duty cycle 455545554555 % notes to table 1?35 : (1) duty cycle distortion specification applies to clock outputs from plls, global clock tree, and ioe driving dedicated and general purpose i/o pins. (2) cyclone iii devices meet sp ecified duty cycle distortion at maximum output toggle rate for each combination of i/o standard and current strength. table 1?36. cyclone iii devices timing specification for series oct with calibration at device power-up (1) symbol description maximum unit t octcal duration of series oct with calibration at device power-up 20 s notes to table 1?36 : (1) oct calibration takes place a fter device configuration, be fore entering user mode. table 1?37. cyclone iii devices ioe programmable delay on column pins (1) , (2) (part 1 of 2) parameter paths affected number of settings min offset max offset unit fast corner slow corner a7, i7 c6 c6 c7 c8 i7 a7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.211 1.314 2.175 2.32 2.386 2.366 2.49 ns input delay from pin to input register pad to i/o input register 8 0 1.203 1.307 2.19 2.387 2.54 2.43 2.545 ns
1?26 chapter 1: cyclone iii device datasheet i/o timing cyclone iii device handbook july 2012 altera corporation volume 2 i/o timing you can use the following methods to determine the i/o timing: the excel-based i/o timing. the quartus ii timing analyzer. the excel-based i/o timing provides pin ti ming performance for each device density and speed grade. the data is typically used prior to designing the fpga to get a timing budget estimation as part of the link timing analysis. the quartus ii timing analyzer provides a more accurate and prec ise i/o timing data based on the specifics of the design after place-and-route is complete. delay from output register to output pin i/o output register to pad 2 0 0.479 0.504 0.915 1.011 1.107 1.018 1.048 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.664 0.694 1.199 1.378 1.532 1.392 1.441 ns notes to table 1?37 : (1) the incremental values for the settings are generally linear. for exact values of each setting, use the latest version of th e quartus ii software. (2) the minimum and maximum offset timing numbers are in refe rence to setting ?0? as availabl e in the quartus ii software. table 1?37. cyclone iii devices ioe programmable delay on column pins (1) , (2) (part 2 of 2) parameter paths affected number of settings min offset max offset unit fast corner slow corner a7, i7 c6 c6 c7 c8 i7 a7 table 1?38. cyclone iii devices ioe programmable delay on row pins (1) , (2) parameter paths affected number of settings min offset max offset unit fast corner slow corner a7, i7 c6 c6 c7 c8 i7 a7 input delay from pin to internal cells pad to i/o dataout to core 7 0 1.209 1.314 2.174 2.335 2.406 2.381 2.505 ns input delay from pin to input register pad to i/o input register 8 0 1.207 1.312 2.202 2.402 2.558 2.447 2.557 ns delay from output register to output pin i/o output register to pad 2 0 0.51 0.537 0.962 1.072 1.167 1.074 1.101 ns input delay from dual-purpose clock pin to fan-out destinations pad to global clock network 12 0 0.669 0.698 1.207 1.388 1.542 1.403 1.45 ns notes to table 1?38 : (1) the incremental values for the settings are generally linear. for exact values of each setting, use the latest version of qu artus ii software. (2) the minimum and maximum offset timing numbers are in refe rence to setting ?0? as availabl e in the quartus ii software
chapter 1: cyclone iii device datasheet 1?27 glossary july 2012 altera corporation cyclone iii device handbook volume 2 f the excel-based i/o timing spreadsheet is downloadable from cyclone iii devices literature website. glossary table 1?39 lists the glossary for this chapter. table 1?39. glossary (part 1 of 5) letter term definitions a ?? b ?? c ?? d ?? e ?? f f hsclk high-speed i/o block: high-speed receiver/transmitter input and output clock frequency. g gclk input pin directly to global clock network. gclk pll input pin to global clock network through pll. h hsiodr high-speed i/o block: maximum/minimum lvds data transfer rate (hsiodr = 1/tui). i input waveforms for the sstl differential i/o standard j jtag waveform k ?? l ?? m ?? v il v ref v ih v swing tdo tck t jpzx t jpco t jsco t jsxz t jph t jsh t jpxz t jcp t jpsu_tms t jcl t jch tdi tms signal to be captured signal to be driven t jpsu_tdi t jszx t jssu
1?28 chapter 1: cyclone iii device datasheet glossary cyclone iii device handbook july 2012 altera corporation volume 2 n ?? o ?? p pll block the following block diagram highlights the pll specification parameters. q ?? r r l receiver differential input discrete resi stor (external to cyclone iii devices). receiver input waveform receiver input waveform for lvds and lvpecl differential standards. rskm (receiver input skew margin) high-speed i/o block: the total margin left a fter accounting for the sampling window and tccs. rskm = (tui ? sw ? tccs) / 2. table 1?39. glossary (part 2 of 5) letter term definitions core clock phase tap reconfigurable in user mode key clk n m pfd vco cp lf clkout pins gclk f i n pfd f i n f vco f out f out _ext switcho v er co u nters c0..c4 single-ended waveform differential waveform (mathematical function of positive & negative channel) positi v e channel (p) = v ih n egati v e channel (n) = v il gro u nd v id v id 0 v v cm p - n v id
chapter 1: cyclone iii device datasheet 1?29 glossary july 2012 altera corporation cyclone iii device handbook volume 2 s single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o standards defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the rece iver input crosses the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the dc threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing . sw (sampling window) high-speed i/o block: the period of time during which the data must be valid to capture it correctly. the setup and hold times determine the ideal strobe position in the sampling window. t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) high-speed i/o block: the timing difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. tcin delay from clock pad to i/o input register. t co delay from clock pad to i/o output. tcout delay from clock pad to i/o output register. t duty high-speed i/o block: duty cycle on high-speed transmitter output clock. t fall signal high-to-low transition time (80?20%). t h input register hold time. timing unit interval (tui) high-speed i/o block: the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c /w). t injitter period jitter on pll clock input. t outjitter_dedclk period jitter on dedicated clock output driven by a pll. t outjitter_io period jitter on general purpose i/o driven by a pll. tpllcin delay from pll inclk pad to i/o input register. tpllcout delay from pll inclk pad to i/o output register. table 1?39. glossary (part 3 of 5) letter term definitions v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
1?30 chapter 1: cyclone iii device datasheet glossary cyclone iii device handbook july 2012 altera corporation volume 2 transmitter output waveform transmitter output waveforms for the lvds, mini-lvds, ppds and rsds differential i/o standards t rise signal low-to-high transition time (20?80%). t su input register setup time. u ?? table 1?39. glossary (part 4 of 5) letter term definitions single-ended waveform differential waveform (mathematical function of positive & negative channel) positi v e channel (p) = v oh n egati v e channel (n) = v ol gro u nd v od v od v od 0 v v os p - n
chapter 1: cyclone iii device datasheet 1?31 glossary july 2012 altera corporation cyclone iii device handbook volume 2 v v cm(dc) dc common mode input voltage. v dif(ac) ac differential input voltage: the minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage: the minimum dc input differential voltage required for switching. v icm input common mode voltage: the common mode of the differential signal at the receiver. v id input differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v ih voltage input high: the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage. v ih(dc) high-level dc input voltage. v il voltage input low: the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il (ac) low-level ac input voltage. v il (dc) low-level dc input voltage. v in dc input voltage. v ocm output common mode voltage: the common mode of the differential signal at the transmitter. v od output differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v od = v oh ? v ol . v oh voltage output high: the maximum positive voltage from an output which the device considers is accepted as the minimum positive high level. v ol voltage output low: the maximum positive voltage from an output which the device considers is accepted as the maximum positive low level. v os output offset voltage: v os = (v oh + v ol ) / 2. v ox (ac) ac differential output cross point voltage: the voltage at which the differential output signals must cross. v ref reference voltage for sstl, hstl i/o standards. v ref (ac) ac input reference voltage for sstl, hstl i/o standards. v ref(ac) = v ref(dc) + noise. the peak-to-peak ac noise on v ref should not exceed 2% of v ref(dc) . v ref (dc) dc input reference voltage for sstl, hstl i/o standards. v swing (ac) ac differential input voltage: ac input differential voltage required for switching. for the sstl differential i/o standard, refer to input waveforms. v swing (dc) dc differential input voltage: dc input differential voltage required for switching. for the sstl differential i/o standard, refer to input waveforms. v tt termination voltage for sstl, hstl i/o standards. v x (ac) ac differential input cross point voltage: the voltage at which the differential input signals must cross. w ?? x ?? y ?? z ?? table 1?39. glossary (part 5 of 5) letter term definitions
1?32 chapter 1: cyclone iii device datasheet document revision history cyclone iii device handbook july 2012 altera corporation volume 2 document revision history table 1?40 lists the revision history for this document. table 1?40. document revision history (part 1 of 3) date version changes july 2012 3.5 updated minimum f hsclk value to 5 mhz. december 2011 3.4 updated ?supply current? on page 1?5 and ?periphery performance? on page 1?17. updated table 1?3, table 1?4, table 1?13, table 1?16, table 1?17, table 1?20, and table 1?25. january 2010 3.3 removed table 1-32 and table 1-33. ad ded literature: external memory interfaces referen ce. december 2009 3.2 minor changes to the text. july 2009 3.1 minor edit to the hyperlinks. june 2009 3.0 changed chapter title from dc and switchi ng characteristics to ?cyclone iii device data sheet? on page 1?1. updated (note 1) to table 1?23 on page 1?17. updated ?external memory interface specifications? on page 1?23. replaced table 1?32 on page 1?23. replaced table 1?33 on page 1?23. added table 1?36 on page 1?26. updated ?i/o timing? on page 1?28. removed ?typical design performance? section. removed ?i/o timing? subsections. october 2008 2.2 updated chapter to new template. updated table 1?1, table 1?3, and table 1?18. added (note 7) to table 1?3. added the ?oct calibration timing specification? section. updated ?glossary? section. july 2008 2.1 updated table 1?38. added blvds information (i/o standard) into table 1?39, table 1?40, table 1?41, table 1?42. updated table 1?43, table 1?46, table 1?47, table 1?48, table 1?49, table 1?50, table 1?51, table 1?52, table 1?53, table 1?54, table 1?55, table 1?56, table 1?57, table 1?58, table 1?59, table 1?60, table 1?61, table 1?62, table 1?63, table 1?68, table 1?69, table 1?74, table 1?75, table 1?80, table 1?81, table 1?86, table 1?87, table 1?92, table 1?93, table 1?94, table 1?95, table 1?96, table 1?97, table 1?98, and table 1?99.
chapter 1: cyclone iii device datasheet 1?33 document revision history july 2012 altera corporation cyclone iii device handbook volume 2 may 2008 2.0 updated ?operating conditions? section and included information on automotive device. updated table 1?3, table 1?6, and table 1?7, and added automotive information. under ?pin capacitance? section, updated table 1?9 and table 1?10. added new ?schmitt trigger input? section with table 1?12. under ?i/o standard specifications? section, updated table 1?13, 1?12 and 1?12. under ?switching characteristics? section, updated table 1?19, 1?15, 1?16, 1?16, 1?17, 1?18, 1?19, 1?20, 1?21, 1?21, 1?23, 1?23, 1?23, 1?24, and 1?25. updated figure 1?5 and 1?29. deleted previous table 1-35 ?ddio outputs half-period jitter?. under ?i/o timing? section, update d table 1?38, 1?29, 1?32, 1?33, 1?26, and 1?26. under ?typical design performance? section updated table 1?46 through 1?145. december 2007 1.5 under ?core performance specifications?, updated tables 1-18 and 1-19. under ?preliminary, correlated, and final timing?, updated table 1-37. under ?typical design performance?, updated tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58, tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, tables 1-87 through 1-92, tables 1-99, 1-100, 1-107, and 1-108. october 2007 1.4 updated the c vreftb value in table 1-9. updated table 1-21. under ?high-speed i/o specification? section, updated tables 1-25 through 1-30. updated tables 1-31 through 1-38. added new table 1-32. under ?maximum input and output clock toggle rate? section, updated tables 1-40 through 1-42. under ?ioe programmable delay? sect ion, updated tables 1-43 through 1-44. under ?user i/o pin timing parameters? section, updated tables 1-45 through 1-92. under ?dedicated clock pin timing parameters? section, updated tables 1-93 through 1- 108. july 2007 1.3 updated table 1-1 with v esdhbm and v esdcdm information. updated r conf_pd information in tables 1-10. added note (3 ) to table 1-12. updated t dlock information in table 1-19. updated table 1-43 and table 1-44. added ?document revision history? section. june 2007 1.2 updated cyclone iii graphic in cover page. table 1?40. document revision history (part 2 of 3) date version changes
1?34 chapter 1: cyclone iii device datasheet document revision history cyclone iii device handbook july 2012 altera corporation volume 2 may 2007 1.1 corrected current unit in tables 1-1, 1-12, and 1-14. added note (3 ) to table 1-3. updated table 1-4 with i ccint0 , i cca0 , i ccd_pll0 , and i ccio0 information. updated table 1-9 and added note (2 ). updated table 1-19. updated table 1-22 and added note (1 ). changed i/o standard from 1.5-v lvttl/lvcmos and 1.2-v lvttl/lvcmos to 1.5-v lvcmos and 1.2-v lvcmos in tabl es 1-41, 1-42, 1-43, 1-44, and 1-45. updated table 1-43 with changes to lvpec and lvds and added note (5 ). updated tables 1-46, 1-47, tables 1-54 th rough 1-95, and tables 1-98 through 1-111. removed speed grade ?6 from tables 1-90 through 1-95, and from tables 1-110 through 1-111. added a waveform (receiver input waveform) in glossary under letter ?r? (table 1-112). march 2007 1.0 initial release. table 1?40. document revision history (part 3 of 3) date version changes

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